1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a high breakdown voltage semiconductor device. The present invention further pertains to a semiconductor device which is usefully employed in a high breakdown voltage EEPROM (Electrically Erasable and Programmable Read-Only Memory) which is under development as a nonvolatile memory of the next generation and which is expected to supplant conventional semiconductor memories such as the PROM (Programmable Read-Only Memory) and EPROM (Erasable and Programmable Read-Only Memory). The present invention is also concerned with a method of manufacturing such a high breakdown voltage semiconductor device.
2. Description of the Related Art
In an EPROM or EEPROM that has a peripheral circuit constituted by a CMOS (Complementary Metal-Oxide Semiconductor) circuit, n-channel MOS (Metal-Oxide Semiconductor) transistors are generally employed to form memory cells. In this case, each memory cell of the EPROM in which data is not electrically erasable is constituted by a single memory transistor, whereas each memory cell of a high breakdown voltage EEPROM in which data is electrically erasable is formed from a combination of a memory transistor and a select transistor (also known as "word transistor") which are coupled together and both of which must generally be n-channel high breakdown voltage transistors.
On the other hand, p-channel MOS type high breakdown voltage transistors in the CMOS peripheral circuit are used only for a voltage changing circuit or the like and therefore the number of p-channel high breakdown voltage transistors required is smaller than the number of n-channel high breakdown voltage transistors used for memory cells.
In particular, in the case of the EEPROM, each memory cell is constituted by a combination of a FAMOS type n-channel transistor used as a memory transistor and a MOS type n-channel MOS transistor used as a select transistor, these two transistors being coupled together at an n-type diffused region which is mutually used as the drain of the memory transistor and the source of the select transistor. The FAMOS type n-channel transistor is formed with a multilayer gate structure wherein a control gate is provided beside a floating gate in which data is written.
The following publications are representative of the above-described prior art that is related to the present invention:
Publication 1: Japanese patent publication No. 58-6237 (1983)
Publication 2: Japanese patent Laid-Open (Kokai) publication No. 59-151469 (1984)
Publication 3: Japanese patent Laid-Open (Kokai) publication No. 61-154078 (1986)
Among the above-mentioned publications, Publication 1 discloses a memory cell for an electrically erasable and programmable nonvolatile semiconductor device, the memory cell being formed using a FAMOS type transistor having a double-layer gate structure. Publication 2 discloses a novel structure for a protective circuit element which is very conformable to a high breakdown voltage MOS type field effect transistor which is defined by a transistor having offset regions provided under either a thick insulating film formed on a substrate or a thick insulating film formed on a part of the surface of a substrate by subjecting it to local oxidation, the offset regions having a lower impurity concentration than the portions of source and drain regions which are in contact with interconnections for leading out the source and drain regions (such a transistor being hereinafter referred to as "LOCOS (Local Oxidation of Silicon) offset type transistor"). Publication 3 discloses a high breakdown voltage MOS type field effect transistor which is defined by a transistor having source and drain regions formed so that each region comprises two regions having different impurity concentrations as in the case of the so-called LDD (Lightly Doped Drain) structure by use of either a resist pattern formed utilizing a mask or a sidewall insulating film formed on each side wall of a gate electrode and that region in each of the source and drain regions which is closer to the channel region and which has a relatively low impurity concentration is defined as an offset region (such a transistor being hereinafter referred to as "masked offset type transistor").
In conventional semiconductor devices of the type described above, that is semiconductor memories having nonvolatile memory cells, two different types of transistor, i.e., p- and n-channel masked offset type transistors and p- and n-channel LOCOS offset type transistors, are produced separately from each other. Accordingly, in a conventional semiconductor device of the type described above, all the p- and n-channel transistors are either masked offset type transistors or LOCOS offset type transistors.
The respective features of the above-mentioned two different types of transistor will next be explained.
The masked offset type transistor occupies a relatively small area and therefore contributes to miniaturization (i.e., achievement of high integration), but on the other hand, it has the disadvantage that a mask or a special process is needed to form the offset regions, that is, it is necessary to carry out a process for forming offset regions which are defined by diffused regions having a relatively low concentration (e.g., p.sup.- or n.sup.-).
In contrast, the LOCOS offset type transistor, which needs to have a thick oxide film above each offset region, requires a relatively large area and is therefore disadvantageous to miniaturization, but it has the advantage that there is no need for a special-purpose mask to form offset regions defined by low concentration (e.g., p.sup.- p.sup.- or n.sup.-) diffused regions and hence the number of required manufacturing steps is smaller than in the case of the masked offset structure.
Accordingly, there is a need for a device structure wherein, in the case where both n- and p-channel transistors are required to have a high breakdown voltage, either of the two types of transistor, that is, n- and p-channel transistors, which is needed in a relatively large number is formed utilizing the masked offset structure, while the other type of transistor, which is not needed in a large number, is formed utilizing the LOCOS offset structure, with the above-described advantages and disadvantages of the two different types of offset structure taken into consideration, and these two types of transistors are appropriately disposed on the same substrate. Development of a method of manufacturing such a device structure is also needed.